This application claims the benefit of Korean Application No. 2000-26767 filed May 18, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display and more particularly, to a method of fabricating liquid crystal display (LCD) device having shorting bars. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for effectively eliminating an electrostatic discharge as well as reducing a fabrication cost in the LCD device.
2. Discussion of the Related Art
As an information technologies rapidly develop, display devices are developed in accordance with the pace of the technology development. The display devices process and display a great deal of information. A cathode ray tube (CRT) has served as a mainstream of the display device area. However, to meet the needs of the current development, a flat panel display device having small size, light weight, and low power consumption is an important subject of research.
A thin film transistor liquid crystal display (TFT LCD) device is an example of the flat panel display devices. The TFT LCD device is very thin and provides superior color display properties. In operation, a thin film transistor serves as a switching element of the TFT LCD device. The thin film transistor of the TFT LCD device switches a pixel such that the pixel controls transmittance of incoming light, which is incident from a back light of the TFT LCD device.
An amorphous silicon layer is widely used for a silicon (active) layer of the thin film transistor. This is because the amorphous silicon layer can be formed on a large, but relatively cheap, glass substrate at a relatively low temperature. The above-mentioned amorphous silicon TFT (a-Si:TFT) is frequently used for thin film transistors.
FIG. 1 is a cross-sectional view illustrating a conventional LCD panel 20. As shown in FIG. 1, the LCD panel 20 has lower and upper substrates 2 and 4 each having a substrate 1 and an interposed liquid crystal layer 10 therebetween.
More specifically, tie lower substrate 2 includes a TFT xe2x80x9cSxe2x80x9d as a switching element to change an orientation of liquid crystal molecules. A pixel electrode 14 formed thereon for applying a voltage to the liquid crystal layer 10 in accordance with the signals from the TFT xe2x80x9cSxe2x80x9d. The upper substrate 4 has a color filter 8 for implementing color. Further, a common electrode 12 is formed on the color filter 8. The common electrode 12 also serves as an electrode for applying a voltage to the liquid crystal layer 10. The pixel electrode 14 is arranged over a unit pixel portion xe2x80x9cPxe2x80x9d, i.e., a display area.
In addition, to prevent leakage of the liquid crystal layer 10 between the lower and upper substrates 2 and 4, the lower and upper substrates 2 and 4 are sealed with a sealant 6. The lower substrate 2 having the TFT xe2x80x9cSxe2x80x9d is referred to as an array substrate since a plurality of TFTs are formed in a shape of matrix.
A plurality of functional thin films including an insulating layer, a silicon layer, and a metal layer are repeatedly deposited and etched to fabricate the above-mentioned TFT LCD device. At this point, an electrostatic discharge must be prevented during the fabricating process for the TFT LCD device. If the electrostatic discharge occurs during the fabricating process, the above-mentioned functional thin films consisting of the thin film transistor xe2x80x9cTFTxe2x80x9d may be damaged.
To prevent the damage due to the above-mentioned electrostatic discharge, shorting bars are adopted for a typical TFT LCD device. The shorting bars are directly connected to each of the gate lines or data lines having a matrix shape such that each line involves an equi-potential with respect to the electrostatic discharge.
Although an amorphous silicon (a-Si:H) layer is widely used for the thin film transistor xe2x80x9cSxe2x80x9d of FIG. 1, a polysilion layer (poly-Si) is recently adopted for the TFT LCD device. FIG. 2 is a plan view illustrating an array substrate 2 of a conventional TFT LCD device adopting the polysilicon layer. As shown in FIG. 2, a plurality of gate lines 30 are transversely formed whereas a plurality of data lines 40 are formed perpendicular to the gate lines 30. Each gate line 30 crosses a corresponding data line 40.
In addition, across one end portion of the gate lines 30, a gate shorting bar 36 is formed to connect each of the gate lines 30. The data lines 40 are also connected with a data shorting bar (not shown) formed across one end portion of the data lines 30. For convenience, the following explanation is focused on the gate shorting bar 36.
The gate shorting bar 36 is not actually used in driving the TFT LCD device. That is to say, the gate shorting bar 36 is etched away once it has performed functions of protecting the TFT LCD device from electrostatic discharge during the fabricating process for the TFT LCD device. Specifically during the final process for fabricating the array substrate 2, the gate shorting bar 36 is broken at a plurality of line opening portions 38 such that first and second gate lines 30a and 30b and the like are independent of each other. The above-mentioned breaking step for he gate shorting bar 36 is usually performed together with the step of forming the TFT xe2x80x9cSxe2x80x9d shown in FIG. 1. A detailed explanation about the above-mentioned gate shorting bar 36 will be provided with reference to FIG. 3 as follows:
FIG. 3 is an expanded plan view of the portion xe2x80x9cAxe2x80x9d shown in FIG 2 and shows a unit pixel region xe2x80x9cPxe2x80x9d of the array substrate 2. The gate line 30 is transversely formed whereas the data line 40 is formed perpendicular to the gate line 30. At the crossing point between the gate and data lines 30 and 40, a thin film transistor xe2x80x9cSxe2x80x9d is formed. The thin film transistor xe2x80x9cSxe2x80x9d has a gate electrode 32, a source electrode 42, a drain electrode 44, and an active layer 50. The gate and source electrodes 32 and 42 are electrically connected with the gate and data lines 30 and 40, respectively.
The drain electrode 44 is spaced apart from the source electrode 42 with a predetermined interval therebetween. In this process, the active layer 50 is made of polysilicon, for example. On the unit pixel region xe2x80x9cPxe2x80x9d defined by the gate and data lines 30 and 40, a pixel electrode 14 is formed thereon. The thin film transistor xe2x80x9cSxe2x80x9d serves to control or switch data signals such that the data signals are applied to the pixel electrode 14.
In addition, the gate shorting line 36 is formed parallel to the data line 40, and is connected to the gate line 30 at one end of the gate line 30. As shown in FIG. 2, the gate shorting line 36 is connected to all of the plurality of gate lines 30 such that the electrostatic discharge is prevented during the fabricating process for the array substrate 2.
After all of the functional thin films are formed for the array substrate 2, the gate shorting line 36 is broken at the line opening portion 38 such that the gate line 30 is electrically independent of the other gate lines (shown in FIG. 2). As shown in FIG. 2, the gate shorting line 36 includes the plurality of line opening portions 38 such that all of the date lines 30 are independent of each other. With reference to FIGS. 4A to 4D, a conventional fabricating process for the array substrate 2 will be explained in detail.
FIGS. 4A to 4D are sequential cross-sectional views taken along the line IV-IV of FIG. 3. In FIG. 4A, a buffer layer 60 and an active layer 50 are sequentially formed on the substrate 1 of the array substrate 2 shown in FIG. 3. The active layer 50 is formed of polysilicon (p-Si), which is achieved via a crystallization process. That is to say, an amorphous silicon layer is deposited on the substrate 1, and then is recrystallized via a laser heat treatment, metal induced crystallization (MIC), and solid phase crystallization (SPC).
Alternatively, polysilicon may be directly deposited on the substrate 1 instead of applying the above-mentioned process. For the laser heat treatment, the substrate including the amorphous silicon layer is heated to about 250 xc2x0 C., and an eximer laser is irradiated to the amorphous silicon layer such that silicon grains are grown from the amorphous silicon. For the MIC, a metal is deposited on the amorphous silicon layer and is used for crystallization. For the SPC, the amorphous silicon layer is heated at a high temperature for a long time such that the polysilicon is formed.
When the substrate 1 is heated during the recrystallization process, alkali metals, usually Na and K and the like included in the substrate 1 may deteriorate properties of the polysilicon layer 50. To avoid such a problem, the buffer layer 60 is formed between the polysilicon layer 50 and substrate to protect the polysilicon layer 50.
In FIG. 4B, a gate-insulating layer 62 is formed on the buffer layer 60 and the active layer 50. The gate-insulating layer 62 is usually selected from the group consisting of silicon oxide (SiO2) and silicon nitride (SiNx). The gate electrode 32 is then formed on the gate-insulating layer 62. The gate electrode 32 includes first and second metal layers 64a and 64b, which are stacked in this order. The first metal layer 64a is made of aluminum (Al) or aluminum alloy (AlNd) each having a low resistance whereas the second metal is 64b is made of molybdenum (Mo), molybdenum and tungsten alloy (MoW), or titanium (Ti)
When the gate electrode 32 is formed, the gate shorting bar 36 is simultaneously formed to have the same layered shape of the first and second metal layers 64a and 64b. After the gate electrode 32 and the gate shorting bar 36 are formed, a doping ion is doped into uncovered portions of the active layer 50, as shown in FIG. 4B. By the above-mentioned ion doping, a contact resistance between the active layer 50 and the source and drain electrodes (reference numeral 42 and 44 in FIG. 4D) which will be formed in the later step is decreased, and the active layer 50 will obtain proper electrical properties. Specifically, after the ion doping, the active layer 50 is divided into a doped region and an intrinsic region 50c. The doped region includes a source region 50a and a drain region 50b. 
For the above-mentioned ion doping, a dopant of Group III or Group V atoms is used. If the Group III atoms are doped into the active layer 50, the active layer 50 becomes n-type semiconductor, whereas if the Group V atoms are doped into, it becomes p-type semiconductor. Phosphorus (P) or boron (B) is usually used as the doping ion.
Next, in FIG. 4C, an interlayer insulating layer 66 is formed on the overall surface of the substrate 1 such that the gate electrode 32 and the active layer 50 are covered. The interlayer insulating layer 66 is formed of the same material as the gate-insulating layer 62. Then, a source contact hole 67a and a drain contact hole 67b are formed through the interlayer insulating layer 66 such that the source and drain regions 50a and 50b are respectively uncovered.
In this process, an etchant is used to form the source and drain contact holes 67a and 67b. When the contact holes 67a and 67b are formed, an opening hole is further formed through the interlayer insulating layer 66 such that a portion of the gate shorting bar 36 is uncovered. Thereafter, the above-mentioned etchant is further used for etching away a portion of the gate shorting bar 36 so as to form the line opening portion 38.
In FIG. 4D, the source and drain electrodes 42 and 44 are formed on the interlayer insulating layer 66. The source and drain electrodes 42 and 44 respectively contact the source and drain regions 50a and 50b via the source and drain contact holes 67a and 67b, respectively. At this time, the data shorting line (not shown) is further formed on the interlayer insulating layer 66.
FIG. 4E illustrates that a passivation layer 68 is formed on the overall surface of the substrate 1 such that the source and drain electrodes 42 and 44 are covered. Through the passivation layer 68, a pixel contact hole 70 is formed such that a portion of the drain electrode 44 is uncovered. Then, the pixel electrode 14 is formed on the passivation layer 68 such that the pixel electrode 14 electrically contacts the drain electrode 44 via the pixel contact hole 70. Portions of the data shorting line are etched away at the time when the pixel contact hole 30 is formed (not shown in FIG. 4E).
As explained in FIGS. 4A to 4E, the gate shorting bar 36 and the data shorting bar (not shown) are formed to directly connect to the gate line 30 and the data line 40, respectively. Thus, the gate and data lines 30 and 40 are protected from an electrostatic discharge. Aster all the functional thin films are formed, the gate and data shorting bars are etched away such that each of the gate and data lines is electrically independent. The etching step or the gate shorting bar 36 will be explained in detail with reference to FIG. 5.
FIG. 5 is an expanded plan view of the portion xe2x80x9cZxe2x80x9d shown in FIG. 4C. As previously explained, in forming the source and drain contact holes 67a and 67b of FIG. 4C, an opening hole is further formed through the interlayer insulating layer 66 such that a portion of the gate shorting bar 36 is uncovered. Then, the uncovered portion of the gate shorting bar 36 is subsequently etched away using the same etchant used for forming the above-mentioned opening hole of the interlayer insulating layer 66.
To form the opening hole for the line opening portion 36, a photoresist xe2x80x9cPRxe2x80x9d is formed on the interlayer insulating layer 66. Then, with the photoresist xe2x80x9cPRxe2x80x9d used as a mask, the open hole 66a is formed through the interlayer insulating layer 66 such that a portion of the gate shorting bar 36 is uncovered. As explained previously, the etchant is used for forming the opening hole 66a of the interlayer-insulating layer 66. A buffered oxide-etching (BOE) solution or a diluted solution of hydrofluoric acid (HF) is usually used as an etchant. Then, the uncovered portion of the gate shorting bar 36 is further etched away using the same etchant such that the line opening portion 38 is formed. Since the same etchant is used for forming the opening hole 66a and the line opening portion 38, the etching process and its equipment may be simplified.
However, the gate shorting bar 36 includes the first and second metal layers 64a and 64b, which are formed of the log resistive aluminum alloy and the relatively harder molybdenum alloy, respectively. As s result, when the above-mentioned etchant is used for etching the gate shorting bar 36, the aluminum alloy is etched well but the molybdenum alloy is not etched away. Therefore, after the etching is finished, the first metal layer 64a corresponding to the line opening portion 38 is etched away but the second metal layer 64b is left in the shape of a bridge along the line opening portion 38.
The second metal layer 64b remained in the line opening portion 38 causes a problem of the conventional LCD device. The non-etched portion of the second metal layer 64b is finally removed in the later process of ashing the photoresist or cleaning the substrate. However, the removed portion of the second metal layer 64b may contaminate the equipment for fabricating the LCD device and serves as an impurity in a photolithography or etching in the later fabrication.
Additional equipment may be used to prevent the above-mentioned problem. However, the additional equipment causes inclination in the cost and the process number in fabricating an LCD device.
Accordingly, the present invention is directed to a method of fabricating a liquid crystal display device having a shorting bar that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an effective method for forming a gate shorting bar.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the intention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of fabricating a liquid crystal display device includes forming first and second metal layers on a substrate, forming a first photoresist layer on the second metal layer, partially removing the first photoresist layer, so that the first photoresist layer has first and second portions, removing the first portion of the first photoresist layer and a portion of the second metal layer, so that a portion of the first metal layer is exposed, forming an insulating layer on the second metal layer including the exposed portion of the first metal layer, forming a second photoresist layer on the insulating layer, removing a portion of the second photoresist layer to expose a portion of the insulating layer, and removing the portion of the insulating layer and first metal layer
In another aspect of the present invention, a method or fabricating a liquid crystal display device, includes forming an active layer on the substrate, forming a gate insulating layer on the active layer, forming a gate shorting bar having first and second metal layer on the gate insulting layer, forming a first photoresist on the second metal layer, partially exposing the first photoresist to light using a mask having a diffraction pattern, ashing the first photoresist and a portion of the second metal layer to expose a portion of the first metal layer, forming an interlayer insulating layer on the gate shorting bar, etching the interlayer insulating layer and the exposed portion of the first metal layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.